With reference to FIGS. 1A and 1B showing respectively a schematic diagram and chip cross section view, a standard DRAM utilizes a charge storage cell for storing a data bit and having a cell access FET (field effect transistor) 1 which has its gate terminal connected to a wordline 3 and its drain terminal connected to a bit line 4. (The actual DRAM chip of course, includes a plurality of such cells arranged in a row/column array.) Capacitor 2 is connected between the source terminal of FET 1 and a voltage source Vbb. In standard DRAM fabrication processes, special processing steps are used to optimize and minimize the capacitor size and the cell size. Such techniques include using higher-capacitance dielectric for the capacitor, special implants to create an FET with higher threshold voltage (V.sub.T), stacked capacitor structure, trench capacitor structure, and combinations of these techniques. However, in standard ASIC (application specific integrated circuit) fabrication processes, no such special processing steps are readily available and the capacitor must be implemented using a standard FET structure. An ASIC process is typically used for logic as compared to memory, and so the standard ASIC FETs are logic-type transistors with relatively low threshold voltage (V.sub.T). In addition, the DRAM cells preferably are placed inside an isolated well to minimize noise disturbances from logic circuit switching and soft error rate due to alpha particle induced carrier generation. No such wells are available using standard ASIC fabrication processes for either the n-channel FET or the p-channel FET of the logic circuit.
In FIGS. 1A, 1B the wordline 3 switches between voltages Vdd and Vbb. However, in a chip fabricated using an ASIC process, the threshold voltage (Vt) for access FET 1 is often not high enough to completely eliminate subthreshold leakage current in the access FET 1 even with the use of voltage Vpp (which is higher than Vdd to introduce backgate effect to increase the Vt level as well as to increase the field threshold voltage associated with field oxide isolation) to bias the n-well.
Other structures shown in FIG. 1B are conventionally the p-doped substrate 8, n-doped well 10, a p doped region 12 which is a drain/source region of FET 1, the upper terminal of capacitor 2 which is "gate" metallization 13, field oxide region 14, n-well contact 16, and field oxide region 18.
Another known implementation, see U.S. Pat. No. 5,600,598 "Memory cell and wordline driver for embedded DRAM in ASIC process" K. Skjaveland and P. Gillingham shown in present FIGS. 2A and 2B, connects the source region 12 of the access FET 1 to the "gate" terminal 13 of the storage capacitor 2 to reduce junction leakage. This patent asserts that negative Vbb D.C. bias is not possible in an ASIC process and a p-channel dynamic wordline driver circuit must be used to generate voltage Vbb in the wordline driver. This configuration also eliminates the need to generate a constant Vbb voltage to bias the gate of the storage capacitor, and the wordline boosted voltage (Vbb) is dynamically generated in the wordline driver circuit. However, this configuration undesirably requires much bigger cell size due to the need to form an interconnection 25 as depicted between the source terminal 12 of the access FET 1 and the gate terminal 13 of the storage capacitor 2.
Structures in FIG. 2B similar to those in FIG. 2A thus have similar reference numbers although they are arranged slightly differently. FIG. 2B additionally shows a second p region 20 to which voltage Vpp is connected and an additional field oxide region 24 separating contact regions 16 and 20. In addition, the wordline 3 still switches between voltages Vdd and Vbb, making it difficult to eliminate subthreshold leakage current in the access FET 1.